Photodetector arrays made from indium gallium arsenide (InGaAs) alloys have been used in many applications, i.e. telecommunications, spectroscopy or imaging to name a few for over 25 years. Depending on the composition of the InxGa1-xAs alloy the detectors can detect light from 500 nm to 2700 nm. The most common composition is In0.53Ga0.47As, which is lattice matched to InP enabling detection from 0.5 um to 1.7 um. These can be manufactured into detector arrays (either one dimensional (1-D) or two dimensional (2-D)), which are then attached to a read out integrated circuit (ROIC) to form a focal plane array. The ROIC converts the charge collected over time to a voltage through amplification. It enables one to measure the amount of light that strikes each pixel in the detector in a given amount of time.
Typically, InGaAs arrays are planar structures with p-i-n (positive-intrinsic-negative) or p-n (positive-negative) photodetector arrays that are monolithic in nature. The detector array has a high bandgap semiconductor (e.g., InP, InAsyP1-y, InxAl1-xAsyP1-y, etc.) above the InxGa1-xAs to minimize dark current and surface recombination from electron hole pairs that form in the detector material. The pixel is formed by diffusing or implanting a p-type dopant like Zn, C, or Be into the structure at certain specific points down to the InxGa1-xAs layer to make the pixel which is a p-i-n or the p-n detector as opposed to doping the entire layer and etching away material to form a mesa structure. An ohmic contact or near ohmic contact is made on top of the diffused area to allow the pixel to be biased and connected to a circuit to remove the charge collected (both dark charge as well as charge from photons that are converted to electron hole pairs). A second contact is made (cathode contact) elsewhere to the n-side material or the substrate , typically InP or InAsyP1-y, to allow the circuit to be completed.
Many conventional techniques have been developed to improve the dark current or the speed of these planar devices. For example, U.S. Pat. No. 6,573,581 describes intentionally doping the intrinsic region of a p-i-n photodiode to reduce the dark current in planar structures. U.S. Pat. No. 4,682,196 describes a structure for making high speed, low dark current devices. Known conventional techniques all require that the photodiode is directly connected to the amplification circuit. U.S. Pat. No. 4,904,608 and/or U.S. Pat. No. 5,242,839 describe lowering the dark current of mesa detector devices. However, mesa devices are isolated from one another physically. In a mesa device the physical isolation prevents cross talk between pixels and causes a loss in some signal and leads to overall higher dark current because the surfaces are not passivated.
U.S. Pat. No. 4,656,494 or U.S. Pat. No. 8,039,882 describes avalanche photodiodes, which have a buried detector layer. The avalanche photodiode attempts to place gain in the detector material to allow for amplification of the signal. The avalanched photodiode, for example, is buried to allow for multiplication of the charge to occur or for a guard ring to be created. The guard ring is to prevent the gain from spreading beyond the avalanche photodiode.
Photodiodes with field effect transistors (FETs) are also known in the art. For example, in U.S. Pat. No. 5,023,686, describes two separate devices developed in one growth that are physically separated by a trench and a non-conductive layer of material. The FET is electrically connected to photodiode through metals and the FET acts as an amplifier. A p-region is buried to further isolate and optimize the FET. U.S. Pat. No. 4,990,990 describes a photodiode with a FET and a waveguide and the FET controls the waveguide which is a different application from creating a low noise imaging application. U.S. Pat. No. 6,005,266 has InGaAs photodiodes integrated with JFETs but these JFETs are for allowing a detector to be turned on or off to determine if it is detecting light. It is for creating a monolithic integrated detector and multiplexer. This does not lower the dark current of the detectors and avoids the need for a ROIC or silicon multiplexer. U.S. Pat. No. 5,386,128 further describes a CCD and an InGaAs photodiode integrated into a single imaging device. The described device moves charge from the photodiode to the integrated amplification circuit. This device specifically requires the photodiode to be directly connected to the amplification circuit and does not use a buried photodiode to reduce the dark current.
In U.S. Pat. No. 5,689,122, a heterojunction bipolar transistor (HBT) is combined with a photodetector on the same substrate to allow for ease of integration. However, the HBT is separated from the photodiode by a trench and they are connected by metal lines or wires. This is not an integrated monolithic device. Pinned photodiodes are conventionally used in most modern Silicon complementary metal-oxide-semiconductor (CMOS) imagers. For example, U.S. Pat. No. 6,297,070 discloses a low noise silicon photodiode that also allows charge transfer similar to a CCD in CMOS devices, thus enabling correlated double sampling in the pixel to lower noise.